VLSI Syllabus
INTRODUCTION TO VLSI
• Need, Scope and History of VLSI.
• Application of VLSI.
• Design Process in VLSI.
• VLSI Design Flow.
INTRODUCTION TO VERILOG HDL
• History of VERILOG HDL.
• Application of VERILOG HDL in Market and Industries.
• Special features of VERILOG HDL.
• Overview of Digital design with VERILOG HDL.
• Operators in VERILOG HDL.
• Data types in VERILOG HDL.
• Blocking and Non Blocking Concept.
DIFFERENT LEVELS IN VERILOG
• Data Flow Level.
• Behavioral Level.
• Structural Level.
• Switch level.
CONDITIONAL STATEMENTS
• If _else statement.
• Case statement.
FINITE STATE MACHINE
• Moore machine.
• Mealy machine.
MINOR PROJECTS
• ALU Design.
• Traffic light Controller.
• Digital Clock.
FPGA HARDWARE INTERFACING
• Introduction to FPGA.
• Working on Physical FPGA.
• Labs on defined topics.
ADVANCES TOPICS IN VERILOG HDL
• Modeling Concepts on Transistor Level.
• Task and Functions.
• User defined primitives.
• Delays in VERILOG.
• VERILOG Test Bench.
• Begin end and Fork-Join Statements.
• Synthesis.
• Timing and Delay Events.
